! ###############################################################
! ###############################################################
! ###                                                         ###
! ###  IOMD system level block models                         ###
! ###                                                         ###
! ###  Created 18/8/92: David Flynn                           ###
! ###                                                         ###
! ###   RAMCTL Main DRAM Control                              ###
! ###                                                         ###
! ###############################################################
! ###############################################################
! ###  Revision History:                                      ###
! ###   28/8/92: AS  : Added RAMCTL                           ###
! ###   02/9/92: AS  : Changed cas to be delayed in writes    ###
! ###   03/9/92: AS  : Added refresh logic & arbiter          ###
! ###   07/9/92: DWF : RAMCTL spilt from IOMDSYS file         ###
! ###   07/9/92: AS  : Moved RAMCR & VREFCR into RAMCTL       ###
! ###   08/9/92: DF  : increased DMADONE setup time           ###
! ###   11/9/92: DF  : refined RAMSM /RAMSMGLUE added         ###
! ###   15/9/92: DF  : export rclkramUS (unsynchronised)      ###
! ###   16/9/92: DF  : armrq renamed busrq with 2nd proc added ##
! ###   17/9/92: AS  : Remove reffsm - use latches instead    ###
! ###   22/9/92  WHO   added dmastart for dag block           ###
! ###  21/12/92: DF  : rclkramUS inverted to RCLKGEN speedup  ###
! ###                  and NINIT->NRESET naming               ###
! ###   7/1/92 : AS  : Removed bank output                    ###
! ###  20/1/93   WO    inverted sense of busrq for speed      ###
! ###  20/1/93 : AS  : Put back Simon's vbusrqram change      ###
! ###  21/1/93 : AS  : Clock reqrqi with falling clk32 before ###
! ###		       synchronising to rclk                  ###
! ###  25/1/93   WO  : changed rclk sync latch to dtype       ###
! ###############################################################

FROM StdParts.PLAs	IMPORT $PLA
FROM StdParts.Misc	IMPORT $BLatch, $SLatch, $NSLatch
FROM StdParts.Misc	IMPORT $Sink, $SDTFF, $Smux
FROM StdParts.Gates	IMPORT $SGate1, $SGate2, $SGate3, $SGate4

FROM iomd.ramctlc	IMPORT $RAMCTLC
FROM iomd.ramsm		IMPORT ramsm
FROM iomd.ramgluepla	IMPORT ramsmglue
FROM iomd.refrsm	IMPORT refrsm
FROM iomd.reffsm	IMPORT reffsm

CONST CASPLA = "iomd/pla/casdecode"


! ###############################################################
! dummy tie offs:

BLOCK SNK({IN} s)
  sink = $Sink(z(s, s))
END {SNK}

BLOCK TBDHI({OUT} s)
  tbdhi = $SGate1(Vdd) => s WITH (delay=1, OP=BUFF)
END {TBDHI}

BLOCK TBDLO({OUT} s)
  tbdlo = $SGate1(Vss) => s WITH (delay=1, OP=BUFF)
END {TBDLO}



! ###############################################################
! IOMD RAMCTL DRAM Controller (RAM/REFRESH statemachines)
! ###############################################################

BLOCK RAMCTL(
  {IN}  rclk,
  {IN}  clk32,
  {IN}  Nreset,
  {IN}  Nbusrq,
  {IN}  dmarq,
  {IN}  dmavbus,
  {IN}  ramgo,
  {IN}  four,
  {IN}  eight,
  {IN}  maxseq,
  {IN}  dmagoing,
  {IN}  dah[28:26],
  {IN}  dal[2:0],
  {IN}  ah[28:26], 
  {IN}  al[2:0],
  {IN}  count0,
  {IN}  ramreg,
  {IN}  progstrb,
  {IN}  la2,
  {IN}  dwrite,
  {IN}  lwrite,
  {IN}  dsize[1:0],
  {IN}  Nbw,
  {IN}  dmach[2:0],
  {IN}  split,
  {IN}  vbusak,
  {IN}  refcres,
  {OUT} cas,
  {OUT} casdel,
  {OUT} dmastart,
  {OUT} vbusrqram,
  {OUT} rclkramUN,  
  {OUT} colmux,
  {OUT} fcolmux, ! Fast column mux control output to ra mux in adec
  {OUT} Ncas[3:0],
  {OUT} Nras[3:0],
  {OUT} Nvras,
  {OUT} Nwe[1:0],
  {OUT} Ndt[1:0],
  {OUT} dsf,
  {OUT} refrq,
  {OUT} dmadone,
  {OUT} ramdmaend,
  {OUT} ramc[2:0],
  {IO}  d[7:0])

busrq = $SGate1(Nbusrq) => busrq WITH (OP=INV, delay=1)

ramsm=RAMSM(
     clk32,
     Nreset,
     ramgo,
     dmagoing,
     busrq,
     wait,
     rburst,
     wburst
   )
   => (ramsmout(
       ramst,
       ras,
       fcolmuxi,
       casi,
       rclkram,
       casdel
       ),
       rclkramUS
     )

rclkramUN = $SGate1(rclkramUS) => rclkramUN WITH (OP=INV, delay=1)

fcolman = $SGate2(fcolmuxi, ras) => fcolmux WITH (op=AND, delay=ns_2)
colmbuf = $SGate1(fcolmux) => colmux WITH (op=BUFF, delay=ns_1)
fourinv = $SGate1(four) => Nfour WITH (op=INV, delay=ns_1)
vbrqram = $SGate2(Nfour, ramst) => vbusrqram WITH (op=OR, delay=ns_2)

ramsmglue=RAMSMGLUE(
     dmarq,
     dmagoing,
     dmach[2:0],
     dmavbus,
     vbusak,
     Nrefwait=vras,
     four,
     eight,
     maxseq,
     lwrite,
     ramstate(
       ramst,
       ras,
       colmux,
       casi,
       rclkram,
       casdel)
   )
   =>  (
     wait,
     rburst,
     wburst,
     ramdmaendz, ! unsynchronised
     refcas
   )

  in1 = $SGate1(dmagoing)            => Ndmagoing WITH (delay=ns_2,OP=INV)
  or1 = $SGate2(Ndmagoing,ramdmaend) => dsi       WITH (delay=ns_2,OP=OR)
  ff1 = $SDTFF(clk32, dsi, Vdd, Vdd) => (dmastart,Ns1) WITH (delay=ns_3, edge=+ve)

  sn1 = SNK(Ns1)

  ramdmaend = $SDTFF(clk32, ramdmaendz, Vdd, Vdd) => (ramdmaend,Nz)
           WITH (delay=ns_2, edge=+ve)

  Nz = SNK(Nz)

  dmadg  = $SGate2(ramdmaend, refdone) => dmadone1 WITH (op=OR, delay=ns_2)

  dmadff = $SDTFF(clk32, dmadone1, Vdd, Vdd) => (dmadone2, Ndmadone2)
           WITH (delay=ns_2, edge=-ve)

  dmadone = $SGate2(dmadone1, dmadone2) => dmadone WITH (op=OR, delay=ns_2)

  ndmads = SNK(Ndmadone2)

  cadl  = $SLatch(Nclk32, casdel) => casid WITH (delay=ns_3)

  casorg  = $SGate2(casi, casid) => cas WITH (op=OR, delay=ns_1)

  caspla = $PLA(Vdd, Vdd, casin(refcas, cas, size[1:0], addll[1:0]))
            => (Ncas[3:0]) WITH (delay=ns_5, filename=CASPLA)

  rclki  = $SGate1(rclk) => Nrclk WITH (op=INV, delay=ns_1)

  refrqi = $SDTFF(clk32, refrqi, Vdd, Vdd) => (refrqid, Nrefrqid)
           WITH (edge=-ve, delay=ns_5)
  refrql = $SDTFF(Nrclk, refrqid, Vdd, Vdd) => (refrq, Nrefrq)
           WITH (edge=+ve, delay=ns_3)
  refrqsnk = SNK(Nrefrqid)
  Nrefrq   = SNK(Nrefrq)

  refrsm = refrsm(
     clk32,
     refcyc=refcas
   )
   =>  (
     ras0,
     ras2,
     vras,
     refdone
   )

  ck32i = $SGate1(clk32) => Nclk32 WITH (op=INV, delay=ns_1)

  ras1l = $SLatch(Nclk32, ras0) => ras1 WITH (delay=ns_3)
  ras3l = $SLatch(Nclk32, ras2) => ras3 WITH (delay=ns_3)

   ramc  = $RAMCTLC(
  {IN}  rclk,
  {IN}  clk32,
  {IN}  Nreset,
  {IN}  dah[28:26],
  {IN}  dal[2:0],
  {IN}  ah[28:26], 
  {IN}  al[2:0],
  {IN}  count0,
  {IN}  ramreg,
  {IN}  progstrb,
  {IN}  la2,
  {IN}  dwrite,
  {IN}  lwrite,
  {IN}  dsize[1:0],
  {IN}  Nbw,
  {IN}  dmagoing, { May go when arbiter implemented }
  {IN}  dmach[2:0],
  {IN}  refcres, { Refresh counter reset from ADEC }
  {IN}  ras,    { From RAM state machine }
  {IN}  cas,
  {IN}  rras(ras3, ras2, ras1, ras0),   { From refresh state machine }
  {IN}  vras,
  {IN}  colmux,
  {IN}  split, { Indicates we're doing a split transfer }
  {IN}  refcyc=refcas,
  {OUT} addll[1:0],
  {OUT} size[1:0], { Only need bits 1 and 0 outside RAMCTLC block }
  {OUT} Nras[3:0],
  {OUT} Nvras,
  {OUT} Nwe[1:0],
  {OUT} Ndt[1:0],
  {OUT} dsf,
  {OUT} refrqi,
  {OUT} ramc[2:0],
  {IO}  d[7:0])

  WITH (delay=(ras=ns_5, cas=ns_5, we=ns_5, dt=ns_5, dsf=ns_3, 
               regs=ns_9, ramc=ns_7))

  sink = $Sink(junk(Ncasid, Ncasid))

END {RAMCTL}
